Copyright (c) 1998, Nicolas Souchu All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or ot...
NAMEiicbus - I2C bus system
SYNOPSISdevice iicbus device iicbb
device iic device ic device iicsmb
DESCRIPTIONThe iicbus system provides a uniform, modular and architecture-independent system for the implementation of drivers to control various I2C devices and to utilize different I2C controllers.
I2CI2C is an acronym for Inter Integrated Circuit bus. The I2C bus was developed in the early 1980's by Philips semiconductors. Its purpose was to provide an easy way to connect a CPU to peripheral chips in a TV-set.
The BUS physically consists of 2 active wires and a ground connection. The active wires, SDA and SCL, are both bidirectional. Where SDA is the Serial DAta line and SCL is the Serial CLock line.
Every component hooked up to the bus has its own unique address whether it is a CPU, LCD driver, memory, or complex function chip. Each of these chips can act as a receiver and/or transmitter depending on its functionality. Obviously an LCD driver is only a receiver, while a memory or I/O chip can both be transmitter and receiver. Furthermore there may be one or more BUS MASTERs.
The BUS MASTER is the chip issuing the commands on the BUS. In the I2C protocol specification it is stated that the IC that initiates a data transfer on the bus is considered the BUS MASTER. At that time all the others are regarded to as the BUS SLAVEs. As mentioned before, the IC bus is a Multi-MASTER BUS. This means that more than one IC capable of initiating data transfer can be connected to it.
DEVICESSome I2C device drivers are available:
- Devices Ta Description
- iic Ta general i/o operation
- ic Ta network IP interface
- iicsmb Ta I2C to SMB software bridge
INTERFACESThe I2C protocol may be implemented by hardware or software. Software interfaces rely on very simple hardware, usually two lines twiddled by 2 registers. Hardware interfaces are more intelligent and receive 8-bit characters they write to the bus according to the I2C protocol.
I2C interfaces may act on the bus as slave devices, allowing spontaneous bidirectional communications, thanks to the multi-master capabilities of the I2C protocol.
Some I2C interfaces are available:
- Interface Ta Description
- pcf Ta Philips PCF8584 master/slave interface
- iicbb Ta generic bit-banging master-only driver
- lpbb Ta parallel port specific bit-banging interface
- bktr Ta Brooktree848 video chipset, hardware and software master-only interface
BUS FREQUENCY CONFIGURATIONThe operating frequency of an I2C bus may be fixed or configurable. The bus may be used as part of some larger standard interface, and that interface specification may require a fixed frequency. The driver for that hardware would not honor an attempt to configure a different speed. A general purpose I2C bus, such as those found in many embedded systems, will often support multiple bus frequencies.
When a system supports multiple I2C busses, a different frequency can be configured for each bus by number, represented by the %d in the variable names below. Busses can be configured using any combination of device hints, Flattened Device Tree (FDT) data, tunables set via loader(8), or at runtime using sysctl(8). When configuration is supplied using more than one method, FDT and hint data will be overridden by a tunable, which can be overridden by sysctl(8).