Copyright (c) 2013, Sean Bruno <firstname.lastname@example.org> All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the docume...
NAMEgpiobus - GPIO bus system
SYNOPSISTo compile these devices into your kernel and use the device hints, place the following lines in your kernel configuration file:
device gpio device gpioc device gpioiic device gpioled
Additional device entries for the ARM architecure include:
device a10_gpio device bcm_gpio device imx51_gpio device lpcgpio device mv_gpio device ti_gpio device gpio_avila device gpio_cambria device zy7_gpio device pxagpio
Additional device entries for the MIPS architecure include:
device ar71xxx_gpio device octeon_gpio device rt305_gpio
Additional device entries for the POWERPC architecure include:
device wiigpio device macgpio
DESCRIPTIONThe gpiobus system provides a simple interface to the GPIO pins that are usually available on embedded architectures and can provide bit banging style devices to the system.
The acronym GPIO means ``General-Purpose Input/Output.''
The BUS physically consists of multiple pins that can be configured for input/output, IRQ delivery, SDA/SCL iicbus use, etc.
On some embedded architechtures (like MIPS), discovery of the bus and configuration of the pins is done via device.hints5 in the platform's kernel config(5) file.
On some others (like ARM), where FDT(4) is used to describe the device tree, the bus discovery is done via the DTS passed to the kernel, being either statically compiled in, or by a variety of ways where the boot loader (or Open Firmware enabled system) passes the DTS blob to kernel at boot.
The following are only provided by the ar71xx_gpio driver.
- This is a bitmask of pins on the gpio board that we would like to expose for use to the host o/s. To expose pin 0, 4 and 7, use the bitmask of 10010001 converted to the hexadecimal value 0x0091.
- This is a bitmask of pins on the gpio board that will be set to ON at host start. To set pin 2, 5 and 13 to be set ON at boot, use the bitmask of 10000000010010 converted to the hexadecimal value 0x2012.
- These are a bitmask of pins that will remap a pin to handle a specific function (USB, UART TX/RX, etc) in the Atheros function registers. This is mainly used to set/clear functions that we need when they are setup or not setup by uBoot.
Simply put, each pin of the GPIO interface is connected to an input/output of some device in a system.