Copyright (c) 2012 The FreeBSD Foundation All rights reserved. This documentation was written by Semihalf under sponsorship from the FreeBSD Foundation. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright...
NAMEnand - NAND Flash framework
DESCRIPTIONThe Fx sysctl Cm net.inet.tcp.syncookies framework consists of a set of interfaces that aim to provide an extensible, object oriented environement for NAND controllers and NAND Flash memory chips from various hardware vendors, and to allow for uniform and flexible management of the NAND devices. It comprises of the following major components:
NAND Flash controller (NFC) interface.
Defines methods which allow to send commands as well as send/receive data between the controller and a NAND chip. Back-end drivers for specific NAND controllers plug into this interface and implement low-level routines for a given NAND controller.
This layer implements basic functionality of a NAND Flash controller. It allows to send command and address to chip, drive CS (chip select line), as well as read/write to the selected NAND chip. This layer is independent of NAND chip devices actually connected to the controller.
NAND chip interface.
Provides basic operations like read page, program page, erase block. Currently three generic classes of drivers are available, which provide support for the following chips:
- large page
- small page
This layer implements basic operations to be performed on a NAND chip, like read, program, erase, get status etc. Since these operations use specific commands (depending on the vendor), each chip has potentially its own implementation of the commands set.
The framework is extensible so it is also possible to create a custom command set for a non standard chip support.
This layer is responsible for enumerating NAND chips in the system and establishing the hierarchy between chips and their supervising controllers.
Its main purpose is detecting type of NAND chips connected to a given chip select (CS line). It also allows manages locking access to the NAND controller. NANDbus passes requests from an active chip to the chip controller.
NAND character / GEOM device.
For each NAND chip found in a system a character and GEOM devices are created which allows to read / write directly to a device, as well as perform other specific operations (like via ioctl).
There are two GEOM devices created for each NAND chip:
- raw device
- normal device
Raw device allows to bypass ECC checking when reading/writing to it, while normal device always uses ECC algorithm to validate the read data.
NAND character devices will be created for each NAND chip detected while probing the NAND controller.