OPENSSL_ia32cap (3)

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NAME

OPENSSL_ia32cap, OPENSSL_ia32cap_loc - the IA-32 processor capabilities vector

SYNOPSIS

 unsigned int *OPENSSL_ia32cap_loc(void);
 #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])

DESCRIPTION

Value returned by OPENSSL_ia32cap_loc() is address of a variable containing processor capabilities bit vector as it appears in register pair after executing instruction with EAX=1 input value (see Intel Application Note #241618). Naturally it's meaningful on x86 and x86_64 platforms only. The variable is normally set up automatically upon toolkit initialization, but can be manipulated afterwards to modify crypto library behaviour. For the moment of this writing following bits are significant:

bit #4 denoting presence of Time-Stamp Counter.

bit #19 denoting availability of

CLFLUSH

instruction;

bit #20, reserved by Intel, is used to choose among

RC4

code paths;

bit #23 denoting

MMX

support;

bit #24,

FXSR

bit, denoting availability of

XMM

registers;

bit #25 denoting

SSE

support;

bit #26 denoting

SSE2

support;

bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;

bit #30, reserved by Intel, denotes specifically Intel CPUs;

bit #33 denoting availability of

PCLMULQDQ

instruction;

bit #41 denoting

SSSE3,

Supplemental

SSE3,

support;

bit #43 denoting

AMD XOP

support (forced to zero on non-AMD CPUs);

bit #57 denoting AES-NI instruction set extension;

bit #59,

OSXSAVE

bit, denoting availability of

YMM

registers;

bit #60 denoting

AVX

extension;

bit #62 denoting availability of

RDRAND

instruction;

For example, clearing bit #26 at run-time disables high-performance

code present in the crypto library, while clearing bit #24 disables code operating on 128-bit register bank. You might have to do the latter if target OpenSSL application is executed on capable but under control of that does not enable registers. Even though you can manipulate the value programmatically, you most likely will find it more appropriate to set up an environment variable with the same name prior starting target application, e.g. on Intel P4 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or better yet 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' to achieve same effect without modifying the application source code. Alternatively you can reconfigure the toolkit with no-sse2 option and recompile.

Less intuitive is clearing bit #28. The truth is that it's not copied from

output verbatim, but is adjusted to reflect whether or not the data cache is actually shared between logical cores. This in turn affects the decision on whether or not expensive countermeasures against cache-timing attacks are applied, most notably in assembler module.

The vector is further extended with

value returned by with EAX=7 and ECX=0 as input. Following bits are significant:

bit #64+3 denoting availability of

BMI1

instructions, e.g.

ANDN

;

bit #64+5 denoting availability of

AVX2

instructions;

bit #64+8 denoting availability of

BMI2

instructions, e.g.

MUXL

and

RORX

;

bit #64+18 denoting availability of

RDSEED

instruction;

bit #64+19 denoting availability of

ADCX

and

ADOX

instructions;