LLVM (http://llvm.org/): LLVM version 4.0.1 Optimized build with assertions. Default target: x86_64-pc-linux-gnu Host CPU: ivybridge

OVERVIEW: llvm-symbolizer USAGE: llvm-symbolizer [options] OPTIONS: General options: -aarch64-neon-syntax - Choose style of NEON code to emit from AArch64 backend: =generic - Emit generic NEON assembly =apple - Emit Apple-style NEON assembly -amdgpu-dump-rtmd - Dump AMDGPU runtime metadata -amdgpu-spill-sgpr-to-smem - Use scalar stores to spill SGPRs if supported by subtarget -amdgpu-vgpr-index-mode - Use GPR indexing mode instead of movrel for vector indexing -arm-execute-only - -arm-implicit-it - Allow conditional instructions outdside of an IT block =always - Accept in both ISAs, emit implicit ITs in Thumb =never - Warn in ARM, reject in Thumb =arm - Accept in ARM, reject in Thumb =thumb - Warn in ARM, emit implicit ITs in Thumb -bounds-checking-single-trap - Use one trap block per function -color - use colored syntax highlighting (default=autodetect) -cvp-dont-process-adds - -default-arch=<string> - Default architecture (for multi-arch objects) -demangle - Demangle function names -disable-spill-fusing - Disable fusing of spill code into instructions -dsym-hint=<string> - Path to .dSYM bundles to search for debug info for the object files -enable-implicit-null-checks - Fold null checks into faulting memory operations -enable-load-pre - -enable-name-compression - Enable name string compression -enable-objc-arc-opts - enable/disable all ARC Optimizations -enable-scoped-noalias - -enable-tbaa - -exhaustive-register-search - Exhaustive Search for registers bypassing the depth and interference cutoffs of last chance recoloring -expensive-combines - Enable expensive instruction combines -filter-print-funcs=<function names> - Only print IR for functions whose name match this for all print-[before|after][-all] options -functions - Print function name for a given address: =none - omit function name =short - print short function name =linkage - print function linkage name -gpsize=<uint> - Global Pointer Addressing Size. The default size is 8. -hash-based-counter-split - Rename counter variable of a comdat function based on cfg hash -ignore-empty-index-file - Ignore an empty index file and perform non-ThinLTO compilation -imp-null-check-page-size=<int> - The page size of the target in bytes -imp-null-max-insts-to-consider=<uint> - The max number of instructions to consider hoisting loads over (the algorithm is quadratic over this number) -inlining - Print all inlined frames for a given address -internalize-public-api-file=<filename> - A file containing list of symbol names to preserve -internalize-public-api-list=<list> - A list of symbol names to preserve -join-liveintervals - Coalesce copies (default=true) -limit-float-precision=<uint> - Generate low-precision inline sequences for some float libcalls -lto-pass-remarks-output=<filename> - Output filename for pass remarks -merror-missing-parenthesis - Error for missing parenthesis around predicate registers -merror-noncontigious-register - Error for register names that aren't contigious -mfuture-regs - Enable future registers -mips-compact-branches - MIPS Specific: Compact branch policy. =never - Do not use compact branches if possible. =optimal - Use compact branches where appropiate (default). =always - Always use compact branches if possible. -mips16-constant-islands - Enable mips16 constant islands. -mips16-hard-float - Enable mips16 hard float. -mno-compound - Disable looking for compound instructions for Hexagon -mno-fixup - Disable fixing up resolved relocations for Hexagon -mno-ldc1-sdc1 - Expand double precision loads and stores to their single precision counterparts -mno-pairing - Disable looking for duplex instructions for Hexagon -mwarn-missing-parenthesis - Warn for missing parenthesis around predicate registers -mwarn-noncontigious-register - Warn for register names that arent contigious -mwarn-sign-mismatch - Warn for mismatching a signed and unsigned value -no-discriminators - Disable generation of discriminator information. -nvptx-sched4reg - NVPTX Specific: schedule for register pressue -obj=<string> - Path to object file to be symbolized (if not provided, object file should be specified for each input line) -pretty-print - Make the output more human friendly -print-address - Show address before line information -print-after-all - Print IR after each pass -print-before-all - Print IR before each pass -print-machineinstrs=<pass-name> - Print machine instrs -print-source-context-lines=<int> - Print N number of source file context -r600-ir-structurize - Use StructurizeCFG IR pass -rdf-dump - -rdf-limit=<uint> - -regalloc - Register allocator to use =default - pick register allocator based on -O option =pbqp - PBQP register allocator =greedy - greedy register allocator =fast - fast register allocator =basic - basic register allocator -rewrite-map-file=<filename> - Symbol Rewrite Map -rng-seed=<seed> - Seed for the random number generator -sample-profile-check-record-coverage=<N> - Emit a warning if less than N% of records in the input profile are matched to the IR. -sample-profile-check-sample-coverage=<N> - Emit a warning if less than N% of samples in the input profile are matched to the IR. -sample-profile-inline-hot-threshold=<N> - Inlined functions that account for more than N% of all samples collected in the parent function, will be inlined again. -sample-profile-max-propagate-iterations=<uint> - Maximum number of iterations to go through when propagating sample block/edge weights through the CFG. -stackmap-version=<int> - Specify the stackmap encoding version (default = 2) -static-func-full-module-prefix - Use full module build paths in the profile counter names for static functions. -stats - Enable statistics output from program (available with Asserts) -stats-json - Display statistics as json data -summary-file=<string> - The summary file to use for function importing. -threads=<int> - -time-passes - Time each pass, printing elapsed time for each on exit -use-symbol-table - Prefer names in symbol table to names in debug info -verify-debug-info - -verify-dom-info - Verify dominator info (time consuming) -verify-loop-info - Verify loop info (time consuming) -verify-loop-lcssa - Verify loop lcssa form (time consuming) -verify-machine-dom-info - Verify machine dominator info (time consuming) -verify-regalloc - Verify during register allocation -verify-region-info - Verify region info (time consuming) -verify-scev - Verify ScalarEvolution's backedge taken counts (slow) -verify-scev-maps - Verify no dangling value in ScalarEvolution's ExprValueMap (slow) -vp-counters-per-site=<number> - The average number of profile counters allocated per value profiling site. -vp-static-alloc - Do static counter allocation for value profiler -x86-asm-syntax - Choose style of code to emit from X86 backend: =att - Emit AT&T-style assembly =intel - Emit Intel-style assembly Generic Options: -help - Display available options (-help-hidden for more) -help-list - Display list of available options (-help-list-hidden for more) -version - Display the version of this program